#### Electrical engineering

• ( 1 ) Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is:

• 1) 0, 1, 3, 7, 15, 14, 12, 8, 0
• 2) 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
• 3) 0, 2, 4, 6, 8, 10, 12, 14, 0
• 4) 0, 8, 12, 14, 15, 7, 3, 1, 0
• Discussion in forum
Answer : 4) 0, 8, 12, 14, 15, 7, 3, 1, 0
Solution : The four bit Johnson's counter connects the complement of the output of the last shift register to the input of the first register with shift distance=1 i.e 1 bit will shift/cycle
It will work as follows:
0000 //Last 0 complemented and fed as input to first register
1000
1100
1110
1111 //Last 1 complemented and fed as input to first register
0111
0011
0001
0000

discussion

Answer : 4) 0, 8, 12, 14, 15, 7, 3, 1, 0

• ( 2 ) The number of min-terms after minimizing the following Boolean expression is _________. [D' + AB' + A'C + AC'D + A'C'D]'

• 1) 1
• 2) 2
• 3) 3
• 4) 4
• Discussion in forum
Answer : 1) 1
Solution : Given Boolean expression is:
[D' + AB' + A'C + AC'D + A'C'D]'
Step 1 : [D' + AB' + A'C + C'D ( A + A')]'
( taking C'D as common )
Step 2 : [D' + AB' + A'C + C'D]'
( as, A + A' = 1 )
: [D' + DC' + AB' + A'C]' (Rearrange)
Step 3 : [D' + C' + AB' + A'C]'
( Rule of Duality, A + A'B = A + B )
: [D' + C' + CA' + AB']' (Rearrange)
Step 4 : [D' + C' + A' + AB']'
(Rule of Duality)
: [D' + C' + A' + AB']' (Rearrange)
Step 5 : [D' + C' + A' + B']'
(Rule of Duality)
:[( D' + C' )'.( A' + B')']
(Demorgan's law, (A + B)'=(A'. B'))
:[(D''.C'').( A''.B'')] (Demorgan's law)
:[(D.C).(A.B)] (Idempotent law, A'' = A)
: ABCD
Hence only 1 minterm after minimization.

discussion

Answer : 1) 1

• ( 3 ) What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate?

• 1) 3
• 2) 4
• 3) 5
• 4) 6
• Discussion in forum
Answer : 2) 4
Solution :

discussion

Answer : 2) 4

• ( 4 ) The function AB'C + A'BC + ABC' + A'B'C + AB'C' is equivalent to

• 1) AC'+AB+A'C
• 2) AB'+AC'+A'C
• 3) A'B+AC'+AB'
• 4) A'B+AC+AB'
• Discussion in forum
Answer : 2) AB'+AC'+A'C
Solution : (A'BC + A'B'C) + (ABC' + AB'C') + AB'C A'C(B + B') + AC'(B + B') + AB'C A'C * 1 + AC' * 1 + AB'C A'C + AC' + AB'C A'C + A(C' + B'C) A'C + A(C' + B') A'C + AC' + AB'

discussion

Answer : 2) AB'+AC'+A'C

• ( 5 ) How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?

• 1) 134
• 2) 133
• 3) 124
• 4) 123
• Discussion in forum
Answer : 4) 123
Solution : 8 bit Counter range 0-255 To go from 10101100 (172) to 00100111 (39)
first counter will move from 172 to 255(255-172 = 83)
255 to 0=1 pulse
and then 0 to 39(39 - 0 = 39)
Total = 83 + 1 + 39 = 123

discussion

Answer : 4) 123

• ( 6 ) What is the minimum number of gates required to implement the Boolean function (AB+C)if we have to use only 2-input NOR gates?

• 1) 2
• 2) 3
• 3) 4
• 4) 5
• Discussion in forum
Answer : 2) 3
Solution : AB+C = (A+C)(B+C) = ((A+C)' + (B+C)')' So, '3' 2-input NOR gates are required.

discussion

Answer : 2) 3

• ( 7 ) The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is

• 1) m2 + m4 + m6 + m7
• 2) m0 + m1 + m3 + m5
• 3) m0 + m1 + m6 + m7
• 4) m2 + m3 + m4 + m5
• Discussion in forum
Answer : 1) m2 + m4 + m6 + m7
Solution :

discussion

Answer : 1) m2 + m4 + m6 + m7

• ( 8 ) Table that lists the inputs for required change of states is called

• 1) truth table
• 2) excitation table
• 3) state table
• 4) clock table
• Discussion in forum
Answer : 2) excitation table
Solution :

discussion

Answer : 2) excitation table

• ( 9 ) The classification of sequential circuit depends on timings of their

• 1) feedback path
• 2) gates
• 3) signals
• 4) complex circuits
• Discussion in forum
Answer : 3) signals
Solution :

discussion

Answer : 3) signals