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    • ( 1 ) The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
      I. Function locals and parameters
      II. Register saves and restores
      III. Instruction fetches

    • 1) I only
    • 2) II only
    • 3) III only
    • 4) I, II and III
    • Discussion in forum
      Answer : 1) I only
      Solution : I is true as by using multiple register windows, we eliminate the need to access the variable values again and again from the memory. Rather, we store them in the registers.
      II is false as register saves and restores would still be required for each and every variable.
      III is also false as instruction fetch is not affected by memory access using multiple register windows.








      discussion


      Answer : 1) I only

    • ( 2 ) A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is _____

    • 1) 5
    • 2) 15
    • 3) 20
    • 4) 25
    • Discussion in forum
      Answer : 3) 20
      Solution : In a k-way set associate mapping, cache memory is divided into sets, each of size k blocks. Size of Cache memory = 16 KB
      As it is 4-way set associative,K = 4
      Block size B = 8 words
      The word length is 32 bits.
      size of Physical address space = 4 GB.
      _________________________________
      No of blocks in Cache Memory(N) = (size of cache memory / size of a block)
      = (16*1024 bytes / 8*4 bytes) = 512 (as 1 word = 4 bytes)
      No of sets(S) = (No of blocks in cache memory/ no of blocks in a set)
      = N/K = 512/4 = 128
      Now,size of physical address = 4GB = 4*(230) Bytes = 232 Bytes
      These physical adresses are divided equally among the sets.
      Hence, each set can access ((232)/128) bytes = 225 bytes = 223 words = 220 blocks
      So, each set can access total of 220 blocks. So to identify these 220 blocks, each set needs TAG bits of length 20 bits








      discussion


      Answer : 3) 20

    • ( 3 ) Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________

    • 1) 1000
    • 2) 10000
    • 3) 100000
    • 4) 100
    • Discussion in forum
      Answer : 2) 10000
      Solution : One request initiation takes 100 ns. As the operations of memory module may overlap in time another, request can be initiated before it completes its remaining 500 ns. Thus total requests that can be initiated is 1000000 ns/100 ns =10000.








      discussion


      Answer : 2) 10000

    • ( 4 ) PSW is saved in stack when there is a _____.

    • 1) interrupt recognized
    • 2) execution of RST instruction
    • 3) Execution of CALL instruction
    • 4) All of these
    • Discussion in forum
      Answer : 1) interrupt recognized
      Solution :








      discussion


      Answer : 1) interrupt recognized

    • ( 5 ) A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is:

    • 1) 1.0 second
    • 2) 1.2 seconds
    • 3) 1.4 seconds
    • 4) 1.6 seconds
    • Discussion in forum
      Answer : 3) 1.4 seconds
      Solution : In the 3rd stage of pipeline, there will be 2 stall cycles i.e. 2 delay slots.
      Total number of instructions = 109
      20% out of 109 are conditional branches.
      Therefore, Cycle penalty = 0.2 * 2 * 109 = 4 * 109
      Clock speed is 1 GHz and each instruction on average takes 1 cycle.
      Total execution time = (109 / 109) + 4 * (108 / 109) = 1.4 seconds
      Thus, total execution time of the program is 1.4 seconds.








      discussion


      Answer : 3) 1.4 seconds

    • ( 6 ) Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h1 while that of the direct mapped one is h2. The value of h2 is:

    • 1) 2.4 ns
    • 2) 2.3
    • 3) 1.8
    • 4) 1.7
    • Discussion in forum
      Answer : 4) 1.7
      Solution : Cache size = 32 KB = 32 * 210 bytes Cache block size = 32 bytes Number of blocks = 1
      Total combinations are : = cache size / (Number of blocks * block size) = 32 * 210 / (1 * 32) = 1024 = 210
      Therefore, number of index bits = 10
      Since, cache block size is 32 bytes i.e. 25 bytes. Number of offset bits = 5
      So, number of tag bits = 32 - 10 - 5 = 17
      Hit latency (h2) = (17 / 10) ns = 1.7 ns








      discussion


      Answer : 4) 1.7

    • ( 7 ) A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor ?

    • 1) Pointers
    • 2) Arrays
    • 3) Records
    • 4) all of these
    • Discussion in forum
      Answer : 4) all of these
      Solution : Pointers require indirect addressing mode. Arrays and records required indexing modes.Recursive procedures with local variable required.








      discussion


      Answer : 4) all of these

    • ( 8 ) Virtual memory is -

    • 1) an extremely large main memory
    • 2) an extremely large secondary memory
    • 3) an illusion of an extremely large memory
    • 4) a type of memory used in super computers
    • Discussion in forum
      Answer : 3) an illusion of an extremely large memory
      Solution :








      discussion


      Answer : 3) an illusion of an extremely large memory

    • ( 9 ) Consider a three word machine instruction
      ADD A[R0], @ B
      The first operand (destination) "A [R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is

    • 1) 3
    • 2) 4
    • 3) 5
    • 4) 6
    • Discussion in forum
      Answer : 2) 4
      Solution : In Indexed addressing mode, the base address is already in the instruction i.e A and to fetch the index data from R0 no memory access is required because it's a register So to fetch the operand only 1 memory cycle is required. Indirect Addressing mode requires 2 memory cycles only








      discussion


      Answer : 2) 4

    • ( 10 ) The function of the ________________ is to store programs and data.

    • 1) CU (Control Unit)
    • 2) MU (Memory Unit)
    • 3) ALU (Arithmetical Logic Unit)
    • 4) INPUT device
    • Discussion in forum
      Answer : 2) MU (Memory Unit)
      Solution :








      discussion


      Answer : 2) MU (Memory Unit)





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